The present invention generally relates to integrated circuit assemblies, and in particular to methods and systems for burn-in screening of integrated circuit assemblies.
Computer systems used for high availability and mission critical applications require highly reliable components and interconnections. Supposedly good components and interconnections can fail prematurely under the stress of normal operation. Removing weak components and interconnections would make systems more reliable. The weaklings can be made to fail by operating them for short periods of time under accelerated conditions—so-called “burn-in.” Once they have failed, the weaklings can be detected and removed before the system is put in service.
Systems and components can be burned-in by operating them at temperatures much higher than normal. This can be done in two ways: by increasing the temperature of the surroundings—“ambient temperature,” or by increasing the power dissipated in the components. Ambient temperature is increased by placing the components or systems in an oven and then increasing the temperature. Power dissipation for MOS devices can be increased by increasing the clock frequency. Thus, increasing clock frequency raises the temperature of MOS integrated circuits. The complex MOS circuits known as DRAMs (Dynamic Random Access Memories) are routinely burned-in.
Some modules containing DRAMs fail early, even though the DRAMs were burned-in before being assembled into modules. These failures may be caused by defects induced by the module assembly process itself. Thus it would be desirable to perform burn-in on the assembled modules.
One disadvantage of module burn-in is its cost, as the memory module industry is quite cost sensitive. Burn-in can be quite expensive, because each module may have to remain at an elevated temperature in a specialized burn-in system for many hours or even days.
Burn-in cost can be reduced by reducing the cost of the burn-in equipment. Cost can be reduced by increasing the chamber ambient temperature to heat the modules, instead of increasing module power dissipation, because increased power dissipation requires expensive power supplies to provide the necessary current. Power supply cost can be reduced even more by operating the modules at lower-than-normal frequencies—say, 20 MHz. Moreover, the lower the clock frequency being used, the less expensive the test equipment required for clock signal generation, and the less expensive the cabling required for clock signal distribution.
Attempts to significantly lower the operating frequency run into a problem. Referring to FIG. 1, a module 100 contains a clock driver 190 that supplies clock frequency in phase to each DRAM 195 on a module. These clock driver circuits contain phase lock loop circuits (PLLs) that operate over a certain frequency range. PLLs cannot lock at lower frequencies, say, below 40 MHz. Thus, what is desired is a way to operate memory modules at frequencies below the minimum PLL lock frequency.